What is the via problem of multilayer PCB board?
Via is one of the important components of multilayer PCB, and the cost of drilling usually accounts for 30% to 40% of the cost of PCB manufacturing. From a design point of view, a via is mainly composed of two parts. One is the drill hole in the middle, and the other is the pad area around the drill. The size of these two parts determines the size of the via. Obviously, in high-speed, high-density PCB design, designers always hope that the smaller the via hole is, the better, so that more wiring space can be left on the board. In addition, the smaller the via hole, the parasitic capacitance of its own. The smaller it is, the more suitable it is for high-speed circuits. However, the reduction in hole size also brings about an increase in cost, and the size of vias cannot be reduced indefinitely. It is limited by process technologies such as drilling and plating: the smaller the hole, the more drilling. The longer the hole takes, the easier it is to deviate from the center position; and when the depth of the hole exceeds 6 times the diameter of the drilled hole, it cannot be guaranteed that the hole wall can be uniformly plated with copper.
Therefore, when comprehensively designing and producing multilayer PCB boards, we need to consider the following issues:
1. In principle, the inner diameter of the full-through hole should be 0.2mm (8mil) and above, and the outer diameter should be 0.4mm (16mil) or more. In difficult places, the outer diameter must be controlled to 0.35mm (14mil);
Notice: According to experience, the inner diameter and outer diameter of PCB commonly used via sizes generally follow X*2±2mil (X represents the inner diameter). For example, vias with an inner diameter of 8mil can be designed as 8/14mil, 8/16mil or 8/18mil; for example, vias with 12mil can be designed as 12/22mil, 12/24mil, 12/26mil;
2. It is recommended not to use buried blind vias for BGA designs of 0.65mm and above, as the cost will increase significantly. When using buried blind holes, generally use first-order blind holes (TOP layer-L2 layer or BOTTOM-negative L2). The inner diameter of the via is generally 0.1mm (4mil) and the outer diameter is 0.25mm (10mil);
3. Vias cannot be placed on pads smaller than the size of the 0402 resistor-capacitance pad; theoretically, the lead inductance is small when placed on the pad. But during production, the solder paste is easy to enter the via, causing uneven solder paste and causing the device to stand up. The phenomenon of getting up (the phenomenon of "stone erecting"). Generally, the recommended spacing is 4-8mil;
4. The distance between vias should not be too close, because drilling is likely to cause holes. Generally, the hole spacing is 0.5mm and above, 0.35mm-0.4mm should be avoided, and 0.3mm and below are prohibited.