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SSD PCB Design Case

[Single board type] SSD solid-state drive

[Pin number] 6213

[Layers] 8 layers

[Maximum rate] 8Gb/s

[Difficulties]:

1. 32 pieces of Nand-flash design, compatible with ONFI and Toggle two protocols;

2. The plate thickness is 1.0mm, the cost is high, and the cascading design is limited;

3. After the simulation, the signal reach to each chip needs the same length;

4. As the number of Nand-flash is relatively large, the heat generation is relatively large too, we need to consider the heat dissipation problem;


[Our countermeasures]:

1. Considering the whole SSD PCB layout, there is almost no wiring space at the top-bottom layer as the structural limited and the layout is tight; according to evaluation, it needs 2-3 inner layers at least for Nand's line, plus other miscellaneous wires and power supplies, the cascade needs to be designed as an 8-layer board and 3 inner layers. and the T-shaped structure is used for routing; the wiring topology and layout are as follows:


SSD PCB Design Case

SSD PCB Design Case


2. Due to considering the customer's batching cost, the number of layers can not be too many, moreover, it should be strictly controlled both of the impedance and the same length on the Nand line and PCIE3.0 on the board. We need to communicate with the customer and SI at the early stage so that the number of layers, wiring equal length and impedance requirements can be satisfied at the same time; The actual design of the cascade is as follows (using an unconventional asymmetric cascade to meet the wiring. the power layer handles some local short signals to meet the reference ground plane):


SSD PCB Design Case


3.5/6 is the design of the adjacent layer, the wiring is staggered. Because the 5th layer processes the DQ signal, there is only a small part of the signal is processed in the 6th layer, the rest large area should be laid the power supply. and ground planes are used for reference reflow; most of the important signals need to be processed at the third level;


4. As the board is thin, in the circumstances of the inner layer does not affect the impedance of the adjacent layer traces, the GND copper is mostly irrigated in the spare place to avoid the board bending;


SSD PCB Design Case


Working Principle of SSD Circuit

Here are three types of SSD circuit working principles.

Over-zero method SSD

As shown in the circuit composition on the previous page, the pedo-zero mode SSD is insulated between input/output by a phototransistor coupler or thyristor coupler. After the input idle signal is set ON, the AC load voltage is triggered near the zero voltage by the built-in over-zero circuit, and the well turns the bidirectional SCR ON.

The voltage and current waveforms for each load are shown below.


● Resistive load

After the input signal is set ON, the AC load voltage and load current become zero, and the SSD is set OFF.


● Inductive load

When the input signal is turned ON, the SSD is turned ON near the zero voltage of the negative Dai voltage, and when the input signal is turned OFF, the SSD is turned OFF when the load current becomes near the zero current, but because of the phase deviation of the voltage and current, a sharp voltage may be applied to the SSD when it is turned OFF. Although the buffer circuit has the effect of suppressing this voltage, if the voltage is too large. The SCR inside the SSD may cause dv/vt malfunction, so care should be taken.


Non-over-zero SSD

The non-zero SSD is insulated between input and output by a silicon controlled coupler. When the input signal is set ON, the output is operated according to the input signal because there is no built-in over-zero circuit. When the input signal is set OFF, the same as the over-zero method, the load current is set OFF in the vicinity of zero current by the blocking action of the bidirectional SCR.


SSD for DC load

The input/output of the SSD for DC load is insulated by a phototransistor coupler. The output transistor is turned ON and OFF by the phototransistor coupler, so the output operates accordingly to the input signal.


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